As is known in this specific technical field, the complex System-on-Chip Integrated Circuits developed use the “Design For Testability” structured technique of the scan chains to allow the Automatic Test Patterns Generation (ATPG) tool to reach the very high standard quality currently required by the customer and, at the same time, reduce the generation time of the patterns.
The currently available scan chain structures, inserted in the device using commercial tools, are built by stitching the device flip-flops to satisfy different constraints such as: minimization of routing (physical scan insertion), minimization of hold time problem, by hierarchical name, and so on.
At the end of the scan chain insertion phase, the structure that normally is inserted resembles the one shown in FIG. 1. The typical connections between two consecutive flip-flops 1 of a scan chain 9 are performed considering one or a combination of the above constraints. Provided that all flip-flops have both a normal output, identified as Q, and an inverted output QN, in some cases Q happens to be connected to the flip-flop input TI of the next flip-flop of the scan chain, while in the other cases the connection is between QN and TI. In other words, the outputs Q or QN of a given flip-flop are linked to the input of the subsequent flip-flop not according to a specific rule, but rather according to the specific requirement or requirements of the specific scan chain.
This limitation does not allow obtaining better performances from a scan chain set up according to the prior art techniques. Extensive analysis has been performed in attempt to find solutions, based on specific algorithms which help in finding the root cause of the problem (e.g. drive mapping method), but they very often require multiple patterns to be run related to the target defect, and specific tools which have to know the whole design structure during the phase in which failure data (obtained during testing phase) are post-processed to get the failure location of the failed device (i.e. an ATPG tool).
The difficulty is that of providing an improved connection configuration having characteristics allowing performing the diagnosis of possible failures while in some cases requiring the knowledge of the scan chain structure only, thus overcoming the limits which still affect the devices realized according to the prior art, and introducing only a small, and often null, area overhead into the hardware structure.